EMC VNX Storage Processor (SP) Cache Configuration
The allocation of read and write cache memory on the VNX Storage Processor (SP) is incorrectly configured when a Storage Administrator adheres to antiquated application recommendations for cache configuration. For example, a table in the Microsoft Technet Exchange Server 2010 TechCenter Library suggests that Storage array cache settings be configured as follows:
|Storage array cache settings||The cache settings are provided by a battery-backed caching array controller.||Best practice: 75 percent write cache and 25 percent read cache (battery-backed cache). Follow storage vendor best practices.|
“Follow storage vendor best practices.” is stated at the end of the cache settings recommendation. Unfortunately most Administrators do not follow storage vendor best practices. Allocating 25 percent to read cache is not an EMC recommendation for the VNX. The EMC Unified Storage Best Practices for Performance and Availability – Applied Best Practices document provides the following recommendations:
- It is always more important to maximize the storage system’s write cache size.
- Always allocate all the remaining memory after system memory is allocated to features and applications to the read/write cache.
- Note that write cache allocation applies to both SPs, it is mirrored. Read cache is not mirrored, to use the available SP memory most efficiently ensure the same amount of read cache is allocated to both storage processors.
- It is advisable to have at least 100 MB of read cache for the block-only VNX5100, and at least 256 MB of read cache for File-enabled systems.
- Only rarely and with serious consideration should more than 10-percent (10%), or more than 1024 MB, of available memory be allocated to the read cache.
- Very few workloads benefit from very large read caches. A 1024 MB read cache is considered a very large read cache.
- Recommended initial Read Cache (MB) – VNX5100 (100 MB), VNX5300 (400 MB), VNX5500 (700 MB), VNX5700 (1024 MB), VNX7500 (1024 MB)
IMPORTANT: Although the document also states, “The amount of memory used by read or write cache can be changed at any time without disruption.”, it is EXTREMELY IMPORTANT to note that in order to make changes to the cache, cache will be disabled. LUNs are still accessible however performance is degraded SIGNIFICANTLY when caching is disabled. DO NOT make changes to the cache configuration casually, schedule a period of time when there will be lower I/O activity to limit the impact of the change.